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                     PRELIMINARY CALL FOR PAPERS
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                    Workshop on Network Processors

                  http://www.cs.washington.edu/NP2/
                         Anaheim, California
                           February 9, 2003


        Held in conjunction with HPCA 9 - The 9th International
         Symposium on High-Performance Computer Architecture
                   http://www.cs.arizona.edu/hpca9/
                         February 8-12, 2003

OVERVIEW

As the performance and importance of digital communication networks
have increased, so have the challenges in network component design. To
meet ever-escalating performance, flexibility and economy
requirements, the networking industry has opted to build products
around network processors. These processors are programmable yet
application-specific; their designs are tailored to efficiently
implement communications applications such as: routing, protocol
analysis, voice and data convergence, firewalls, VPNs, and QoS. The
term network processor is used here in the most generic sense -- from
task-specific processors, such as classification and encryption
engines, to more general-purpose packet or communications processors.

Network processor design is an emerging field with numerous challenges
and opportunities. The goal of this workshop is to provide a forum for
engineers and scientists from academia and industry to discuss their
latest research in the architecture, design, programming, and use of
these devices. We are especially interested in attracting new or
experimental techniques and approaches. 

IMPORTANT DATES

Papers due : November 1, 2002
Notification to authors : January 6, 2003

TOPICS

Topics of particular interest include, but are not limited to:

    * Architectures for network, communications, or packet processors
    * Network Processor theory of design
    * Novel commercial product designs
    * Search engines
    * Benchmarking and performance analysis
    * Coprocessors such as CAMs and other support devices
    * Interfaces to high-speed packet buses and switch fabrics
    * Techniques for accelerating network services
    * Voice processing and packet telephony
    * Software aspects of programming processors for networking
    * Applications, including packet forwarding, packet classification, 
      QoS, encryption and security, compression, etc.

The workshop will consist of a keynote address, paper presentations
and a panel session. In addition to academic and research
contributions, product descriptions that focus on architecture
(hardware or software) or performance analysis will also be
considered. Attendees will receive a copy of workshop papers. After
the workshop, selected papers will be published in a book entitled
Network Processor Design: Issues and Practices Volume II (Morgan
Kaufman Publishers).  

SUBMISSIONS

Please submit full papers (single spaced, font size 11, 1 inch
margins, not exceeding 15 pages) in Adobe PDF format for review to
pcrowley@cs.washington.edu.

NOTES FROM NP1 (2002):

Selected papers from NP1 and additional industry contributions will
appear in Network Processor Design : Issues and Practices Volume I
(Morgan Kaufmann Publishers, September 2002).

ORGANIZERS

Patrick Crowley, University of Washington (pcrowley@cs.washington.edu)
Mark Franklin, Washington University in St. Louis (jbf@ccrc.wustl.edu)
Haldun Hadimioglu, Polytechnic University (haldun@photon.poly.edu)
Peter Z. Onufryk, IDT (peter.onufryk@idt.com)

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